Yield Enhancement Layer Optimizer

Cut PCB engineering and fabrication costs with YELO

Ucamco’s brand-new suite of Yield Enhancing Layout modules guarantees lowest cost PCB fabrication by optimising board layout for client-specified manufacturing class, delivering higher-yield, easy to manufacture designs, and cutting CAM throughput times by up to 30%. For a limited time, YELO is available free of charge for evaluation in UcamX 2018.06, the latest version of Ucamco’s ultra-powerful all-in-one CAM software suite for the global PCB manufacturing industry.

Gent, Belgium – September 25th, 2018 – Ucamco is delighted to introduce YELO, its brand-new suite of Yield Enhancing Layout modules. With high-speed multichannel intelligence, YELO automates one of the most cumbersome tasks in PCB pre-production by scanning PCB designs for design conflicts, anomalies and potential problems, and generating alternative design solutions on the fly.

PCB manufacturers always check their customers’ incoming design data in detail prior to manufacture, using tools such as the UcamX Design Rule Check (DRC) module. More often than not, such checks highlight multiple problems, typically violations of customer-specified track widths and clearances or feature parameters, of which the CAD designer may well be unaware, and which inevitably place the PCB in a higher and more expensive manufacturing class, made even more expensive by the higher risk of scrap. Having found the issues, the manufacturer has two choices: capabilities permitting, the customer can be quoted a higher price to make the product "as is", or, and this is where CAM engineers spend most of their time, the violations are resolved one by one, by moving features, changing track widths and other parameters, and trying to bring the product back within the client’s originally stated lower cost manufacturing class, going through multiple DRC iterations to ensure that new problems have not been created in the process. It’s a complex and time-consuming undertaking, and done manually, it is far from optimal: the engineer will typically try to resolve issues by making changes in the immediate vicinity, but the optimal solution may require a series of changes that start much further away.

This is where YELO comes in. Its Copper Adjuster Signal and Plane modules scan the entire board, and with an impressive arsenal of intelligent automated correction functionality, they shift and alter tracks, copper dams, annular rings and other features on signal, plane and mixed layers throughout the board to ensure that issues are resolved optimally, reliably, and according to customer and manufacturer design rules, to bring the PCB design within stated class and specifications while maintaining netlist integrity. Similarly, YELO Legend Adjuster scans and adjusts the size and positioning of legend as necessary.

And it’s all done with unprecedented speeds and range, says Ucamco’s Dirk Leroy: "Using combinational decisions, YELO makes multiple ‘yes/no’ decisions in parallel, making it faster and smarter than the human brain. It examines numerous iterations simultaneously, and backtracks if decisions turn out to be less than optimal."

And where the designer’s authorisation is needed to sanction changes, YELO makes a copy of a given copper layer to document the ‘before and after’ design situations, facilitating faster, easier comunication and design turnaround times.

Ucamco is currently offering YELO free of charge for evaluation in its latest UcamX 2018.06 software distribution, together with a number of other improvements including better error reporting for Design Rules, enhanced import of Eagle fonts and customisable Rout Path Sequence. It also allows users to read UcamX jobs straight out of zip archives, as well as displaying PCB top and bottom layers in realistic colours.